1. Field of the Invention
The present invention relates to a MOS transistor formation method in a semiconductor device. More particularly, the present invention relates to a MOS transistor formation method, in which, during formation of a MOS transistor, when a refresh time is improved by blocking phosphorus out diffusion and improving electric field by means of an oxide film side wall after forming a landing plug contact (LPC), an oxide film side wall on a silicon (Si) surface is eliminated and an electric current path is induced to the surface so as to compensate for electric current reduction due to increase of LDD resistance, so that a write margin of a cell transistor can be improved.
2. Description of the Prior Art
A MOS transistor formation method according to the prior art will be described with reference to FIGS. 1a to 1d. 
FIGS. 1a to 1d are sectional views according to steps in the MOS transistor formation method according to the prior art.
In the MOS transistor formation method according to the prior art, as shown in FIG. 1a, an isolation layer 13 for isolating a device region is formed in a silicon substrate 11. Then, a gate electrode 21 including a gate oxide film 15, a polysilicon layer 17, and a hard mask layer 19 is formed on the device region of the silicon substrate 11.
Next, an oxidation process is carried out to form an oxide film 23 on one side wall of a polysilicon layer 17 constituting the gate electrode 21 and an upper surface of the silicon substrate 11.
Subsequently, an LDD implanting is carried out to form an LDD implant region 25 in an active region of the silicon substrate 11 below the oxide film 23.
Then, a buffer oxide film 27 and a nitride film acting as a spacer 29 are sequentially deposited on an upper surface of overall structure inclusive of the oxide film 23, and an anisotropic etching process is carried out to selective eliminate the nitride film acting as the spacer 29, the buffer oxide film 27, and the oxide film 23. Therefore, the spacer 29 is formed on a side surface of the gate electrode 21. Herein, a portion of the active region in the silicon substrate 11 is exposed while the spacer 29 is formed.
Subsequently, an interlayer dielectric film 31 is thickly deposited on an upper surface of overall structure inclusive of the exposed active region in the silicon substrate 11.
Next, as shown in FIG. 1b, a photosensitive film pattern is formed in order to form a landing plug contact hole 33 in the interlayer dielectric film 31, and the interlayer dielectric film 31 and the active region portion in the silicon substrate 11 are over-etched using the photosensitive film pattern as a mask. Thereby, the landing plug contact hole 33 is formed. Herein, a portion of the silicon substrate 11 is also etched away when the landing plug contact hole 33 is formed.
Subsequently, as shown in FIG. 1c, the photosensitive film pattern is eliminated, and then a landing plug side wall oxide film 35 is formed on a surface of overall structure inclusive of the landing plug contact hole 33.
Next, the landing plug side wall oxide film 35 is anisotropically dry-etched so that the landing plug side wall oxide film 35 remains only on a side wall of the landing plug contact hole 33.
Subsequently, as shown in FIG. 1d, a polysilicon layer is deposited on an upper surface of overall structure inclusive of the landing plug contact hole 33 to fill in the landing plug contact hole 33.
Next, the polysilicon layer is planarized through a CMP process to form a landing plug 37 in the landing plug contact hole 33.
However, in a structure of a conventional MOS transistor, according to the reduction of a design rule, the thickness of a cell spacer nitride film is reduced, and the out-diffusion of phosphorus of high concentration from a landing plug polysilicon layer increases. Therefore, electric field of a cell transistor increases, thereby degrading refresh time.
When the phosphorus out-diffusion is blocked by means of a landing plug oxide film side wall in order to improve the refresh time, electric current is reduced due to increase of LDD resistance. Therefore, a write margin of the cell transistor is reduced.